Conventionally, a lateral-type semiconductor device in which a trench-gate-type IGBT is formed and an electric current flows in a planar direction of a substrate has been proposed, for example, in a patent literature 1. In this semiconductor device, in particular, a P-type base layer is formed in a surface layer portion of an N−-type drift layer, and an N+-type emitter layer is formed in a surface layer portion of the base layer. Further, a plurality of trenches each of which passes through the base layer and the emitter layer and reaches the drift layer are extended in one direction. A gate insulation film and a gate electrode are orderly formed on a wall surface of each trench. It is to be noted that this trench does not reach a rear surface of the drift layer.
An emitter electrode is provided on the base layer and the emitter layer through an interlayer insulation film. The emitter electrode is electrically connected to the base layer and the emitter layer through contact holes formed in the interlayer insulation film. A P+-type collector layer is formed in the surface layer portion of the drift layer at a position separated from the base layer. Specifically, this collector layer is disposed in the drift layer adjacent to a side wall of the trench. Namely, a distance between the side wall of each trench and the collector layer is different. Further, a collector electrode is provided on the collector layer.
In such a semiconductor device, when a predetermined gate voltage is applied to the gate electrode, an N-type channel region is formed in the base layer at a portion adjoining the trench. When electrons are supplied from the emitter layer to the drift layer through the channel region and holes are supplied from the collector layer to the drift layer, a resistance value falls due to conductivity modulation and thus the semiconductor device becomes in an on state.